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19-1105; Rev 0; 8/96
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
_______________General Description
The MAX534 serial-input, voltage-output, 8-bit quad digital-to-analog converter (DAC) operates from a single +4.5V to +5.5V supply. Internal precision buffers swing rail to rail, and the reference input range includes both ground and the positive rail. The MAX534 features a 2.5A shutdown mode. The serial interface is double buffered: a 12-bit input shift register is followed by four 8-bit buffer registers and four 8-bit DAC registers. The 12-bit serial word consists of eight data bits and four control bits (for DAC selection and special programming commands). Both the input and DAC registers can be updated independently or simultaneously with a single software command. Two additional asynchronous control pins, LDAC and CLR, provide simultaneous updating or clearing of the input and DAC registers. The interface is compatible with SPITM, QSPITM (CPOL = CPHA = 0 or CPOL = CPHA = 1), and MicrowireTM. A buffered data output allows daisy chaining of serial devices. In addition to 16-pin DIP and CERDIP packages, the MAX534 is available in a 16-pin QSOP that occupies the same area as an 8-pin SO. For operation guaranteed to 2.7V, see the MAX533 data sheet.
____________________________Features
o +4.5V to +5.5V Single-Supply Operation o Ultra-Low Supply Current: 0.8mA while Operating 2.5A in Shutdown Mode o Ultra-Small 16-Pin QSOP Package o Ground to VDD Reference Input Range o Output Buffer Amplifiers Swing Rail to Rail o 10MHz Serial Interface Compatible with SPI, QSPI (CPOL = CPHA = 0 or CPOL = CPHA = 1), and Microwire o Double-Buffered Registers for Synchronous Updating o Serial Data Output for Daisy Chaining o Power-On Reset Clears Serial Interface and Sets All Registers to Zero o Software Shutdown o Software-Programmable Logic Output (C I/O Extender) o Asynchronous Hardware Clear Resets All Internal Registers to Zero
MAX534
________________________Applications
Digital Gain and Offset Adjustments Programmable Attenuators Programmable Current Sources Portable Instruments
______________Ordering Information
PART MAX534ACPE MAX534BCPE MAX534ACEE MAX534BCEE MAX534BC/D MAX534AEPE MAX534BEPE MAX534AEEE MAX534BEEE MAX534AMJE MAX534BMJE TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP Dice* 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CERDIP** 16 CERDIP** INL (LSB) 1 2 1 2 2 1 2 1 2 1 2
__________________Pin Configuration
TOP VIEW
OUTB 1 OUTA 2 REF 3 UPO 4 PDE 5 LDAC 6 CLR 7 DOUT 8 16 OUTC 15 OUTD 14 AGND
MAX534
13 VDD 12 DGND 11 DIN 10 SCLK 9 CS
*Dice are tested at TA = +25C. **Contact factory for availability and processing to MIL-STD-883. Functional Diagram appears at end of data sheet.
DIP/QSOP
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534
ABSOLUTE MAXIMUM RATINGS
VDD to DGND ..............................................................-0.3V, +6V VDD to AGND...............................................................-0.3V, +6V Digital Input Voltage to DGND ....................................-0.3V, +6V Digital Output Voltage to DGND....................-0.3V, (VDD + 0.3V) AGND to DGND ..................................................................0.3V REF ................................................................-0.3V, (VDD + 0.3V) OUT_ ...........................................................................-0.3V, VDD Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.53mW/C above +70C) .........842mW QSOP (derate 8.3mW/C above +70C) .....................667mW CERDIP (derate 10.00mW/C above +70C) ..............800mW Operating Temperature Ranges MAX534 _ C_ E ..................................................0C to +70C MAX534 _ E_ E ...............................................-40C to +85C MAX534 _ MJE .............................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +4.5V to +5.5V, VREF = 4.096V, AGND = DGND = 0V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25C.) PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Zero-Code Error Zero-Code-Error Supply Rejection Zero-Code Temperature Coefficient Full-Scale Error Full-Scale Error Supply Rejection Full-Scale Temperature Coefficient REFERENCE INPUTS Input Voltage Range Input Resistance Input Capacitance Channel-to-Channel Isolation AC Feedthrough DAC OUTPUTS Output Voltage Range Load Regulation RL = open Code = FF hex, measured with IL = 0mA to 1.6mA 0 VREF 0.156 V LSB/mA (Note 2) (Note 3) 0 322 460 10 -60 -60 VDD 598 V k pF dB dB INL DNL ZCE MAX534A MAX534B Guaranteed monotonic (all codes) Code = 00 hex Code = 00 hex, VDD = 4.5V to 5.5V Code = 00 hex Code = FF hex Code = FF hex, VDD = 4.5V to 5.5V Code = FF hex 10 10 30 1 8 1 2 1.0 20 1 Bits LSB LSB mV LSB V/C mV LSB V/C SYMBOL CONDITIONS MIN TYP MAX UNITS
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +4.5V to +5.5V, VREF = 4.096V, AGND = DGND = 0V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25C.) PARAMETER DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage-Output Slew Rate Output Settling Time Digital Feedthrough and Crosstalk Digital-to-Analog Glitch Impulse Signal-to-Noise Plus Distortion Ratio Multiplying Bandwidth Wideband Amplifier Noise POWER SUPPLIES Power-Supply Voltage Supply Current Shutdown Current VDD IDD MAX534C/E MAX534M 4.5 0.8 0.8 2.5 5.5 1.3 1.5 10 V mA A SINAD CODE = FF hex To 1/2LSB, from code 00 to code FF hex (Note 5) VREF = 0V, code 00 to code FF hex (Note 6) Code 80 hex to code 7F hex VREF = 4Vp-p at 1kHz, code = FF hex VREF = 4Vp-p at 10kHz VREF = 0.5Vp-p, 3dB bandwidth 0.6 8 5 50 80 70 380 60 V/s s nV-s nV-s dB kHz VRMS VOH VOL ISOURCE = 0.2mA ISINK = 1.6mA VDD - 0.5 0.4 V V VIH VIL IIN CIN VIN = 0V or VDD (Note 4) 0.7VDD 0.3VDD 1.0 10 V V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX534
TIMING CHARACTERISTICS
(VDD = +4.5V to +5.5V, VREF = 4.096V, AGND = DGND = 0V, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25C.) PARAMETER VDD Rise to CS Fall Setup Time (Note 4) LDAC Pulse Width Low CS Rise to LDAC Fall Setup Time (Note 7) CLR Pulse Width Low CS Pulse Width High SYMBOL tVDCS tLDAC tCLL tCLW tCSW MAX534C/E MAX534M MAX534C/E MAX534M MAX534C/E MAX534M MAX534C/E MAX534M MAX534C/E MAX534M 40 50 40 50 40 50 90 100 20 25 20 25 CONDITIONS MIN TYP MAX 50 60 UNITS s ns ns ns ns
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534
TIMING CHARACTERISTICS (continued)
(VDD = +4.5V to +5.5V, VREF = 4.096V, AGND = DGND = 0V, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25C.) PARAMETER SERIAL-INTERFACE TIMING SCLK Clock Frequency (Note 8) SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN to SCLK Rise to Setup Time DIN to SCLK Rise to Hold Time SCLK Rise to DOUT Valid Propagation Delay (Note 9) SCLK Fall to DOUT Valid Propagation Delay (Note 10) SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Setup Time fCLK tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 MAX534C/E MAX534M MAX534C/E MAX534M MAX534C/E MAX534M MAX534C/E MAX534M 40 50 40 50 MAX534C/E MAX534M MAX534C/E MAX534M MAX534C/E MAX534M MAX534C/E MAX534M MAX534C/E MAX534M 40 50 40 50 40 50 0 40 50 0 200 230 210 250 10 8.3 MHz ns ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: INL and DNL are measured with RL referenced to ground. Nonlinearity is measured from the first code that is greater than or equal to the maximum offset specification to code FF hex (full scale). See DAC Linearity and Voltage Offset section. Note 2: VREF = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting one DAC's code to FF hex and setting all other DAC's codes to 00 hex. Note 3: VREF = 4Vp-p, 10kHz. DAC code = 00 hex. Note 4: Guaranteed by design, not production tested. Note 5: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of VOUT's final value. Note 6: Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC. Note 7: If LDAC is activated prior to CS's rising edge, it must stay low for tLDAC or longer after CS goes high. Note 8: When DOUT is not used. If DOUT is used, fCLK max is 4MHz, due to the SCLK to DOUT propagation delay. Note 9: Serial data clocked out at SCLK's rising edge (measured from 50% of the clock edge to 20% or 80% of VDD). Note 10: Serial data clocked out at SCLK's falling edge (measured from 50% of the clock edge to 20% or 80% of VDD).
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
__________________________________________Typical Operating Characteristics
(VDD = +5V, TA = +25C, unless otherwise noted.)
DAC ZERO-CODE OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
MAX534-TOC1
MAX534
DAC FULL-SCALE OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT
DAC FULL-SCALE OUTPUT VOLTAGE (V)
MAX534-TOC2
SUPPLY CURRENT vs. TEMPERATURE
DAC CODE = FF HEX 800 SUPPLY CURRENT (A)
MAX534-TOC3
1.50 DAC ZERO-CODE OUTPUT VOLTAGE (V) 1.25 1.00 0.75 0.50 0.25 0 0 1 2 3 4 5 6 7 VREF = 5V DAC CODE = 00 HEX LOAD TO VDD
5.0 4.5 4.0 3.5 3.0 2.5 2.0 VREF = 5V DAC CODE = FF HEX LOAD TO GND 0 2 4 6 8 10
1000
600 DAC CODE = 00 HEX
400
200 VREF = 4.5V 0 12 -55 -35 -15 5 25 45 65 85 105 125
8
DAC OUTPUT SINK CURRENT (mA)
DAC OUTPUT SOURCE CODE (mA)
TEMPERATURE (C)
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX534-TOC4
SUPPLY CURRENT vs. REFERENCE VOLTAGE
MAX534-TOC6
5 SHUTDOWN SUPPLY CURRENT (A)
1000 ALL DAC CODES = FF HEX
3
800 SUPPLY CURRENT (A)
3
600 ALL DAC CODES = 00 HEX
2
400
1 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
200 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V)
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME OUTB OUTA REF UPO PDE LDAC CLR DOUT CS SCLK DIN DGND VDD AGND OUTD OUTC DAC B Voltage Output DAC A Voltage Output Reference-Voltage Input Software-Programmable Logic Output Power-Down Enable. Must be high to allow software shutdown mode. Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents of each input latch to its respective DAC latch. Clear DAC Input (active low). Driving CLR low asynchronously clears the input and DAC registers, and sets all DAC outputs to zero. Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the rising or falling edge of SCLK (Table 1). Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming commands are executed when CS returns high. Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling (default) or rising edge (A0 = A1 = 1, see Table 1). Serial Data Input. Data is clocked in on the rising edge of SCLK. Digital Ground Power Supply, +4.5V to +5.5V Analog Ground DAC D Voltage Output DAC C Voltage Output FUNCTION
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534
INSTRUCTION EXECUTED
CS
***
SCLK DIN A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 MSB DACA DOUT MODE 1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 LSB
*** ***
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 MSB DACD D1 D0 LSB
***
A1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1
DATA FROM PREVIOUS DATA INPUT DOUT MODE 0 (DEFAULT)
DATA FROM PREVIOUS DATA INPUT
***
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1
Figure 1. 3-Wire Interface Timing
CS tCS0 SCLK tDS tDH DIN tD02 tD01 DOUT tCSS tCL tCH tCP tCSH
tCSW tCS1
tCLL LDAC
tLDAC
Figure 2. Detailed Serial-Interface Timing Diagram _______________________________________________________________________________________
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534
_______________Detailed Description
Serial Interface
At power-on, the serial interface and all digital-toanalog converters (DACs) are cleared and set to code zero. The serial data output (DOUT) is set to transition on SCLK's falling edge. The MAX534 communicates with microprocessors through a synchronous, full-duplex, 3-wire interface (Figure 1). Data is sent MSB first and can be transmitted in one 4-bit and one 8-bit (byte) packet or in one 12-bit word. If a 16-bit word is used, the first four bits are ignored. A 4-wire interface adds a line for LDAC and allows asynchronous updating. The serial clock (SCLK) synchronizes the data transfer. Data is transmitted and received simultaneously. Figure 2 shows the detailed serial-interface timing. Please note that the clock should be low if it is stopped between updates. DOUT does not go into a highimpedance state if the clock idles or CS is high. Serial data is clocked into the data registers in MSB-first format, with the address and configuration information preceding the actual DAC data. Data is clocked in on SCLK's rising edge while CS is low. Data at DOUT is clocked out 12 clock cycles later, either at SCLK's falling edge (default or mode 0) or rising edge (mode 1). Chip select (CS) must be low to enable the DAC. If CS is high, the interface is disabled and DOUT remains unchanged. CS must go low at least 40ns before the first rising edge of the clock pulse to properly clock in the first bit. With CS low, data is clocked into the MAX534's internal shift register on the rising edge of the external serial clock. Always clock in the full 12 bits because each time CS goes high the bits currently in the input shift register are interpreted as a command. SCLK can be driven at rates up to 10MHz.
Serial Input Data Format and Control Codes The 12-bit serial input format shown in Figure 3 comprises two DAC address bits (A1, A0), two control bits (C1, C0), and eight bits of data (D7...D0). The 4-bit address/control code configures the DAC as shown in Table 1. Load Input Register, DAC Registers Unchanged (Single Update Operation)
A1 A0 Address (LDAC = H) C1 0 C0 1 D7 D6 D5 D4 D3 D2 8-Bit Data D1 D0
When performing a single update operation, A1 and A0 select the respective input register. At the rising edge of CS, the selected input register is loaded with the current shift-register data. All DAC outputs remain unchanged. This preloads individual data in the input register without changing the DAC outputs.
Load Input and DAC Registers
A1 A0 Address (LDAC = H) C1 1 C0 1 D7 D6 D5 D4 D3 D2 8-Bit Data D1 D0
This command directly loads the selected DAC register at CS's rising edge. A1 and A0 set the DAC address. Current shift-register data is placed in the selected input and DAC registers. For example, to load all four DAC registers simultaneously with individual settings (DAC A = 1V, DAC B = 2V, DAC C = 3V, and DAC D = 4V), four commands are required. First, perform three single input register update operations for DACs A, B, and C (C1 = 0). The final command loads input register D and updates all four DAC registers from their respective input registers.
Software "LDAC " Command
THIS IS THE FIRST BIT SHIFTED IN MSB DOUT A1 A0 C1 C0 D7 D6 A1 LSB D1 D0 DIN 0 A0 1 C1 0 C0 0 D7 x D6 x D5 x D4 x D3 x D2 x D1 x D0 x
...
(LDAC = 1)
CONTROL AND ADDRESS BITS
8-BIT DAC DATA
When this command is initiated, all DAC registers are updated with the contents of their respective input registers at CS's rising edge. With the exception of using CS to execute, this performs the same function as the asynchronous LDAC.
Figure 3. Serial Input Format
8 _______________________________________________________________________________________
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534
Table 1. Serial-Interface Programming Commands
12-BIT SERIAL WORD A1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 1 C1 0 0 0 0 1 1 1 1 0 C0 1 1 1 1 1 1 1 1 0 D7 . . . . . . . . D0 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data XXXXXXXX
LDAC
1 1 1 1 1 1 1 1 1
FUNCTION Load input register A; all DAC outputs unchanged. Load input register B; all DAC outputs unchanged. Load input register C; all DAC outputs unchanged. Load input register D; all DAC outputs unchanged. Load input register A; all DAC outputs updated Load input register B; all DAC outputs updated Load input register C; all DAC outputs updated Load input register D; all DAC outputs updated. Software LDAC commands. Update all DACs from their respective input registers. Also bring the part out of shutdown mode. Load all DACs with shift-register data. Also bring the part out of shutdown mode. Software shutdown (provided PDE is high) UPO goes low. UPO goes high. No operation (NOP); shift data in shift registers. Set DOUT phase--SCLK rising (mode 1). DOUT clocked out on rising edge of SCLK. All DACs updated from their respective input registers. Set DOUT phase--SCLK falling (mode 0). DOUT clocked out on falling edge of SCLK. All DACs updated from their respective registers (default).
1 1 0 0 0 1
0 1 0 1 0 1
0 0 1 1 0 1
0 0 0 0 0 0
8-bit DAC data XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
X X X X X X
1
0
1
0
XXXXXXXX
X
Load All DACs with Shift-Register Data
A1 1 A0 0 C1 0 C0 0 D7 D6 D5 D4 D3 D2 8-Bit Data D1 D0
User-Programmable Output (UPO)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 1 0 0 x x x x x x x x x x x x x x x x UPO Output Low High
(LDAC = X)
When this command is initiated, all four DAC registers are updated with shift-register data. This command allows all DACs to be set to any analog value within the reference range. It can be used to substitute CLR if code 00 hex is programmed, which clears all DACs.
(LDAC = X)
Software Shutdown
A1 1 A0 1 C1 0 C0 0 D7 x D6 x D5 x D4 x D3 x D2 x D1 x D0 x
This command initiates the user-programmable logic output for controlling another device across an isolated interface. Example devices are gain control of an amplifier and a polarity output for a motor speed control.
No Operation (NOP)
A1 0 A0 0 C1 0 C0 0 D7 x D6 x D5 x D4 x D3 x D2 x D1 x D0 x
(LDAC = X, PDE = H)
This command shuts down all output buffer amplifiers, reducing supply current to 10A max.
(LDAC = X)
The NOP command (no operation) allows data to be shifted through the MAX534 shift register without affecting the input or DAC registers. This is useful in daisy chaining (also see the Daisy Chaining Devices section).
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534
For this command, the data bits are "Don't Cares." As an example, three MAX534s are daisy chained (A, B, and C), and devices A and C need to be updated. The 36-bit-wide command would consist of one 12-bit word for device C, followed by an NOP instruction for device B and a third 12-bit word with data for device A. At CS's rising edge, device B will not change state.
Set DOUT Phase--SCLK Rising (Mode 1)
A1 1 A0 1 C1 1 C0 0 D7 x D6 x D5 x D4 x D3 x D2 x D1 x D0 x
Serial Data Output DOUT is the internal shift register's output. DOUT can be programmed to clock out data on SCLK's falling edge (mode 0) or rising edge (mode 1). In mode 0, output data lags input data by 12.5 clock cycles, maintaining compatibility with Microwire and SPI. In mode 1, output data lags input data by 12 clock cycles. On power-up, DOUT defaults to mode 0 timing. DOUT never three-states; it always actively drives either high or low and remains unchanged when CS is high.
(LDAC = x)
The mode 1 command resets the serial-output DOUT to transition at SCLK's rising edge. Once this command is issued, DOUT's phase is latched and will not change except on power-up or if the specific command to set the phase to falling edge is issued. This command also loads all DAC registers with the contents of their respective input registers, and is identical to the "LDAC" command.
SCLK
SK SO MICROWIRE PORT
MAX534 DIN
CS
I/0
Set DOUT Phase--SCLK Falling (Mode 0, Default)
A1 1 A0 0 C1 1 C0 0 D7 x D6 x D5 x D4 x D3 x D2 x D1 x D0 x
(LDAC = x)
This command resets DOUT to transition at SCLK's falling edge. The same command also updates all DAC registers with the contents of their respective input registers, identical to the "LDAC" command.
Figure 4. Connections for Microwire
LDAC Operation (Hardware) LDAC is typically used in 4-wire interfaces (Figure 7). This command is level sensitive, and allows asynchronous hardware control of the DAC outputs. With LDAC low the DAC registers are transparent, and any time an input register is updated, the DAC output immediately follows. Clear DACs with CLR Strobing the CLR pin low causes an asynchronous clear of input and DAC registers and sets all DAC outputs to zero. Similar to the LDAC pin, CLR can be invoked at any time, typically when the device is not selected (CS = H). When the DAC data is all zeros, this function is equivalent to the "Update all DACs from Shift Registers" command.
MAX534 DIN
SCLK CS
MOSI SCK I/0
SPI/QSPI PORT
Figure 5. Connections for SPI/QSPI
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
Interfacing to the Microprocessor The MAX534 is MicrowireTM and SPITM/QSPITM compatible (Figures 4 and 5). For SPI and QSPI, clear the CPOL and CPHA configuration bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA = 1 configuration can also be used if the DOUT output is ignored. The MAX534 can interface with Intel's 80C5X/80C3X family in mode 0 if the SCLK clock polarity is inverted. More universally, if a serial port is not available, three lines from one of the parallel ports can be used for bit manipulation. Digital feedthrough at the voltage outputs is greatly minimized by operating the serial clock only to update the registers. The clock idle state is low. Daisy-Chaining Devices Any number of MAX534s can be daisy-chained by connecting DOUT of one device to DIN of the following device in the chain. The NOP instruction (Table 1) allows data to be passed from DIN to DOUT without changing the input or DAC registers of the passing device. A 3-wire interface updates daisy-chained or individual MAX534s simultaneously by bringing CS high (Figure 6).
Analog Section
DAC Operation The MAX534 uses a matrix decoding architecture for the DACs, which saves power in the overall system. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor string presents a code-independent input impedance to the reference and guarantees a monotonic output. Figure 8 shows a simplified diagram of the four DACs. Reference Input The voltage at REF sets the full-scale output voltage for all four DACs. The 460k typical input impedance at REF is code independent. The output voltage for any DAC can be represented by a digitally programmable voltage source as follows: VOUT = (NB x VREF) / 256 where NB is the numerical value of the DAC's binary input code.
MAX534
MAX534
SCLK DIN CS SCLK DIN CS DEVICE A DOUT SCLK DIN CS
MAX534
SCLK DOUT DIN CS DEVICE B
MAX534
DOUT
DEVICE C
TO OTHER SERIAL DEVICES
SCLK DIN CS
SCLK DIN CS
MAX534
Figure 6. Daisy-chained or individual MAX534s are simultaneously updated by bringing CS high. Only three wires are required.
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534
DIN SCLK LDAC CS1 CS2 CS3 TO OTHER SERIAL DEVICES
CS LDAC MAX534 SCLK DIN
CS LDAC MAX534 SCLK DIN
CS LDAC MAX534 SCLK DIN
Figure 7. Multiple MAX534s sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling an individual CS.
REF R0 R1 R15
D7 R16 D6 D5 D4 MSB DECODER
Output Buffer Amplifiers All MAX534 voltage outputs are internally buffered by precision unity-gain followers that slew at about 0.6V/s. The outputs can swing from GND to VDD. With a 0V to +4V (or +4V to 0V) output transition, the amplifier outputs will typically settle to 1/2LSB in 8s when loaded with 10k in parallel with 100pF. The buffer amplifiers are stable with any combination of resistive (10k) or capacitive loads.
R255
LSB DECODER D3 D2 D1 D0
DAC A
Figure 8. DAC Simplified Circuit Diagram
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+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
__________Applications Information
DAC Linearity and Voltage Offset
The output buffer can have a negative input offset voltage that would normally drive the output negative, but since there is no negative supply the output stays at 0V (Figure 9). When linearity is determined using the endpoint method, it is measured between zero code (all inputs 0) and full-scale code (all inputs 1) after offset and gain error are calibrated out. However, in singlesupply operation the next code after zero may not change the output, so the lowest code that produces a positive output is the lower endpoint. Careful PC board layout minimizes crosstalk among DAC outputs and digital inputs. Figure 10 shows suggested circuit board layout to minimize crosstalk.
MAX534
Unipolar-Output, Two-Quadrant Multiplication
In unipolar operation, the output voltages and the reference input are the same polarity. Figure 11 shows the MAX534 unipolar configuration, and Table 2 shows the unipolar code.
SYSTEM GND
Power Sequencing
The voltage applied to REF should not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REF and VDD to ensure compliance with the absolute maximum ratings. Do not apply signals to the digital inputs before the device is fully powered up.
OUTC OUTD AGND
OUTB OUTA REF
Power-Supply Bypassing and Ground Management
Connect AGND and DGND together at the IC. This ground should then return to the highest-quality ground available. Bypass VDD with a 0.1F capacitor, located as close to VDD and DGND as possible.
Figure 10. Suggested PC Board Layout for Minimizing Crosstalk (Bottom View)
REFERENCE INPUT 3 REFAB +3V 13 VDD
MAX534
2 DAC A OUTA
OUTPUT VOLTAGE DAC B SERIAL INTERFACE NOT SHOWN 0V NEGATIVE OFFSET DAC CODE
1 OUTB
16 DAC C OUTC
15 DAC D DGND 12 OUTD AGND 14
Figure 9. Effect of Negative Offset (Single Supply)
Figure 11. Unipolar Output Circuit
13
______________________________________________________________________________________
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534
Table 2. Unipolar Code Table
DAC CONTENTS MSB 1111 LSB 1111 ANALOG OUTPUT +VREF 255 256 +VREF 129 256 +VREF 128 256 +VREF +VREF
(----)
1000
0001
(----)
V
1000
0000
REF (----) = + ---- 2
0111
1111
127 (----) 256 1 (----) 256
0000 0000
0001 0000
0V
1 Note: 1LSB = (VREF) (2-8) = +VREF (----) 256
_________________________________________________________Functional Diagram
DOUT CLR LDAC UPO PDE VDD REF DGND AGND
DECODE CONTROL INPUT REGISTER A
MAX534
OUTA DAC REGISTER A DAC A
OUTB 12-BIT SHIFT REGISTER INPUT REGISTER B DAC REGISTER B DAC B
OUTC INPUT REGISTER C DAC REGISTER C DAC C
OUTD SR CONTROL INPUT REGISTER D DAC REGISTER D DAC D
CS
DIN
SCLK
14
______________________________________________________________________________________
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
___________________Chip Information
TRANSISTOR COUNT: 6821
MAX534
________________________________________________________Package Information
DIM INCHES MILLIMETERS MAX MIN MIN MAX 0.068 0.061 1.55 1.73 0.004 0.0098 0.127 0.25 0.061 0.055 1.40 1.55 0.012 0.008 0.20 0.31 0.0075 0.0098 0.19 0.25 SEE VARIATIONS 0.157 0.150 3.81 3.99 0.25 BSC 0.635 BSC 0.244 0.230 5.84 6.20 0.016 0.010 0.25 0.41 0.035 0.016 0.41 0.89 SEE VARIATIONS SEE VARIATIONS 8 0 0 8 DIM PINS D S D S D S D S 16 16 20 20 24 24 28 28 INCHES MILLIMETERS MIN MAX MIN MAX 0.189 0.196 4.80 4.98 0.0020 0.0070 0.05 0.18 0.337 0.344 8.56 8.74 0.0500 0.0550 1.27 1.40 0.337 0.344 8.56 8.74 0.0250 0.0300 0.64 0.76 0.386 0.393 9.80 9.98 0.0250 0.0300 0.64 0.76
21-0055A
D A e B
A1
S
A A1 A2 B C D E e H h L N S
E
H h x 45 A2
N E C L
QSOP QUARTER SMALL-OUTLINE PACKAGE
______________________________________________________________________________________
15
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534
________________________________________________________Package Information
DIM INCHES MIN MAX - 0.200 0.014 0.023 0.038 0.065 0.008 0.015 0.220 0.310 0.290 0.320 0.100 0.125 0.200 0.150 - 0.015 0.070 - 0.098 0.005 - MILLIMETERS MIN MAX - 5.08 0.36 0.58 0.97 1.65 0.20 0.38 5.59 7.87 7.37 8.13 2.54 3.18 5.08 3.81 - 0.38 1.78 - 2.49 0.13 -
E1 A D E
Q L e B S1 S B1 L1
0-15 C
A B B1 C E E1 e L L1 Q S S1
CERDIP CERAMIC DUAL-IN-LINE PACKAGE (0.300 in.)
DIM PINS D D D D D D 8 14 16 18 20 24
INCHES MILLIMETERS MIN MAX MIN MAX - 0.405 - 10.29 - 0.785 - 19.94 - 0.840 - 21.34 - 0.960 - 24.38 - 1.060 - 26.92 - 1.280 - 32.51
21-0045A
E D A3 A A2 E1
DIM A A1 A2 A3 B B1 C D1 E E1 e eA eB L
L A1 e B D1
0 - 15 C B1 eA eB
INCHES MAX MIN 0.200 - - 0.015 0.175 0.125 0.080 0.055 0.022 0.016 0.065 0.045 0.012 0.008 0.080 0.005 0.325 0.300 0.310 0.240 - 0.100 - 0.300 0.400 - 0.150 0.115 INCHES MIN MAX 0.348 0.390 0.735 0.765 0.745 0.765 0.885 0.915 1.015 1.045 1.14 1.265
MILLIMETERS MIN MAX - 5.08 0.38 - 3.18 4.45 1.40 2.03 0.41 0.56 1.14 1.65 0.20 0.30 0.13 2.03 7.62 8.26 6.10 7.87 2.54 - 7.62 - - 10.16 2.92 3.81 MILLIMETERS MIN MAX 8.84 9.91 18.67 19.43 18.92 19.43 22.48 23.24 25.78 26.54 28.96 32.13
21-0043A
Plastic DIP PLASTIC DUAL-IN-LINE PACKAGE (0.300 in.)
PKG. DIM PINS P P P P P N D D D D D D 8 14 16 18 20 24
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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